1. Field of the Invention
This invention relates to high gain, high frequency amplifier circuits.
More particularly, this invention relates to circuits that compensate for changes and fluctuations in the gain of high gain, high frequency amplifier circuits due environmental factors such as manufacturing process, temperature, and operating conditions.
2. Description of Related Art
The basic structure of a differential amplifier well known in the art and is generally as shown in FIG. 1. The n-type metal oxide semiconductor (NMOS) transistors M1 and M2 are generally coupled at their sources and connected to the current source IB. The drains of the NMOS transistors M1 and M2 are respectively connected to the equal valued load resistors RL1 and RL2. The gates of the NMOS transistors Ml and M2 are respectively connected to the input terminals IN1 and IN2. The drain currents of the NMOS transistors M1 and M2 are summed and must be equal to the current of the current source IB. It can thus be shown that the voltage present at the drain of the NMOS transistors M1 and M2 is equal to:
xe2x80x83VOUTd=xe2x88x92gmRLnVlNd
where:
VOUTd is the differential voltage at the output nodes OUT1 and OUT2.
gm is the transconductance of the NMOS transistors M1 and M2.
RLn is the resistance of the resistors RL1 or RL2.
VINd is the differential voltage at the input nodes IN1 and IN2.
The variations in the differential voltage VOUTd due to variations in the environmental factors such as temperature, process parameters, and operating conditions can be shown to effect the values of the transconductance gm of the NMOS transistors M1 and M2 and the dependence of the resistors RL1 and RL2 to the environmental factors. One method for compensation of these variations is to place the source degeneration resistors Rs1 and Rs2 respectively in the source connections of the NMOS transistors M1 and M2. The source degeneration resistors Rs1 and Rs2 have resistance designs to sufficiently improve the immunity of the differential amplifier to the variations, but not impact the dynamic range of the output voltage VOUTd.
The effective transconductance gms of the NMOS transistors M1 and M2 in combination with the source degeneration resistors Rs1 and Rs2 can be shown to be equal to:                               g          ms                =                              g            m                                1            +                                          g                m                            ⁢              Rs                                                          Eq        .                  xe2x80x83                ⁢        1            
Further, the gain of the differential amplifier is then expressed as:                     Av        =                                            V              OUTd                                      V              INd                                =                                    g              ms                        ⁢                          RL              n                                                          Eq        .                  xe2x80x83                ⁢        2            
As is known the appropriate choices of the materials for the resistors Rs1 and Rs2 and the resistors RL1 and RL2 minimize the effects of the environmental factors. However, this does not stabilize the gain completely.
As the gain requirements for an amplifier increases, multiple differential amplifiers of FIG. 1 are cascaded as shown in FIG. 2. The first differential stage Av1 of the cascaded amplifier is formed of the NMOS transistors M20 and M21, the load resistors RL3 and RL4, the current source IB1, and the source degeneration resistors Rs1 and Rs2 configured as shown in FIG. 1. The second differential stage Av2 of the cascaded amplifier is formed of the NMOS transistors M22 and M23, the load resistors RL5 and RL6, the current source IB2, and the source degeneration resistors RS3 and Rs4, also configured as shown in FIG. 1. Similarly, the third differential stage AV3 of the cascaded amplifier is formed of the NMOS transistors M24 and M25, the load resistors RL7 and RL8, the current source IB3, and the source degeneration resistors Rs5 and Rs6, which are configured as shown in FIG. 1. The input nodes IN1 and IN2 are coupled by capacitors CP1 and CP2 to the gates of the NMOS transistors M20 and M21. The bias resistors RB1 and RB2 provide a biasing voltage from the biasing voltage power supply VGG to bias the amplifier Av1 to operate in a linear, high gain region. The output terminals of the amplifier Av1 are coupled through the capacitors CP3 and CP4 to the gates of the NMOS transistors M22 and M23. As described for the bias resistors RB1 and RB2, the bias resistors RB3 and RB4 provide a biasing voltage from the biasing voltage power supply VGG to bias the amplifier Av2 to operate in a linear, high gain region. Next, the output terminals of the amplifier Av2 are coupled through the capacitors CP5 and CP6 to the gates of the NMOS transistors M24 and M26. As described for the bias resistors RB1 and RB2 and the bias resistors RB3 and RB4, the bias resistors RB5 and RB6 provide a biasing voltage from the biasing voltage power supply VGG to bias the amplifier Av3 to operate in a linear, high gain region. The output signal of the amplifier is coupled through the capacitors CP7 and CP8 to the output terminals OUT1 and OUT2. The gain of the amplifier of FIG. 2 is the product of the individual gains of the differential amplifier stages Av1, Av2, and Av3 and are determined as defined above for the amplifier described in FIG. 1. Further, the number of differential amplifier stages Av1, Av2, and Av3 is determined by the total gain required for the amplifier, thus the design of the individual stages may vary to accommodate the design requirements.
As described above the source degeneration resistors Rs3Rs4, Rs5 and Rs6, Rs7 and Rs8 are added to partially compensate for the variations in the environmental factors. Further, other compensation techniques employ feedback to adjust the gain of the differential amplifier stages with changes in the environmental factors. However, feedback techniques do not work well when very large gain factors are required for the amplifier. In Analog Integrated Circuit Design, Johns and Martin, John Wiley and Sons, Inc., New York, 1999, pp. 248-251, the author notes that the transconductance of the NMOS transistors of a differential amplifier is the most important parameter to stabilize. The authors detail and analyze basic techniques to prevent variations of the transconductance with variations in the environmental factors.
U.S. Pat. No. 6,018,270 (Stuebing, et al.) describes a single biasing circuit for a single or multiple stage low voltage RF circuits including one or more amplifiers and one or more single or double balanced mixers. The biasing circuit incorporates compensation for temperature and integrated circuit process parameters.
U.S. Pat. No. 4,409,558 (Knijnenburg, et al.) describes a gain compensated transistor amplifier arrangement for use in power protection circuits. The amplifier includes an emitter-follower transistor. The collector current of the emitter-follower transistor is fed to a resistor to compensate for variations in the current gain factor of the transistors of the amplifier.
U.S. Pat. No. 4,916,407 (Olver) illustrates a gain variation compensating circuit for a feed-forward linear amplifier. The gain compensating circuit counteracts the gain variations and restores balance and fundamental cancellation to the circuit while retaining the highly linear characteristics of the amplifier.
U.S. Pat. No. 5,274,339 (Wideman, et al.) teaches circuit for compensating for GaAs FET amplifier gain variations over a frequency band as a function of temperature. The circuit includes a passive equalizer circuit having a fixed gain over the frequency band and an active equalizer circuit, in series with the passive equalizer, having a gain, which varies over the frequency band as a function of temperature.
U.S. Pat. No. 6,046,642 (Brayton, et al.) describes an active bias compensation circuit that senses a quiescent current flowing in an amplifier and adjusts the quiescent current to maintain an optimal DC biasing of the amplifier over a wide range of temperature variation, process variation, history of the amplifier, etc.
U.S. Pat. No. 5,673,047 (Moreland) describes a gain compensating difterential reference circuit that is used to match the gain of an input differential amplifier that is an input of an analog-to-digital converter to provide a biasing voltage to the analog-to-digital converter.
U.S. Pat. No. 4,929,909 (Gilbert) teaches a single differential amplifier including a current source for generating a biasing tail current to compensate for the non-ideal transistor geometries and properties. The compensation results in an amplification ratio, which is substantially independent of all component variations.
U.S. Pat. No. 5,994,961 (Lunn, et al.) teaches an amplifier circuit that has a gain control input signal to adjust the gain of the amplifier. The gain control input signal is passed through a temperature compensating circuit, which provides a gain compensation to adjust the gain of the amplifier for temperature. The gain of the amplifier is adjusted as desired, however, the amplifier gain is compensated for temperature variations.
An object of this invention is to provide a gain compensation circuit that compensates for variations in gain of a high gain, high frequency amplifier.
Another object of this invention is to provide a circuit that adjusts biasing currents of a high gain, high frequency amplifier to compensate fully for changes in mobility of transistor and resistor components of the amplifier.
To accomplish at least one of these objects and other objects, a gain compensation circuit includes a current adjustment circuit and a gain factor evaluation circuit. The current adjustment circuit modifies a bias current provided to each amplifier stage of a plurality of amplifier stages that make up a high gain, high frequency amplifier. The modification of the bias current adjusts the gain factor of the amplifier. The gain factor evaluation circuit is in communication with the current adjustment circuit to determine changes in the gain factor of the high gain, high frequency amplifier. From the determination, the gain factor evaluation circuit provides a compensation signal to the current adjustment circuit indicating a modification factor for the biasing current for each amplifier stage.
In a first embodiment of this invention, the current adjustment circuit has a first reference constant current source mirrored from a reference current source to generate a reference current. A first replica amplifier is connected to the first reference constant current source to conduct a master biasing current that is modified according to the compensation signal. Biasing currents for each amplifier is provided by a plurality of mirroring current sources. Each mirroring current source is in communication with the first replica amplifier stage such that each mirroring current sources generates one bias current proportional to the master bias current of the replica amplifier stage.
In a second and third embodiment of this invention, the current adjustment circuit is a plurality of mirroring current sources. The mirroring current sources provide the bias currents for each amplifier stage. The mirroring current sources receive the compensating signal from the gain factor evaluation circuit. In this embodiment, the compensating signal is a compensation current from which the bias currents are mirrored.
The gain factor evaluation circuit has a reference voltage source to provide a first and a second reference voltage, which are inputs to a second replica amplifier stage. The second replica amplifier stage amplifies a voltage difference between the first and the second reference voltages. The gain factor evaluation circuit has a compensation signal generator connected to the second replica amplifier stage to receive the amplified voltage difference, modulate a biasing current of the second replica amplifier stage and, when the amplified voltage difference approaches a null level, produce the compensation signal. The compensation signal generator is formed of an operational amplifier having an in-phase input and an out-of-phase input connected to receive the amplified voltage difference. The compensation signal generator has a first master current source that provides the biasing current to the second replica amplifier and a second master current source joined to the out-of-phase input of the operational amplifier. The second master current source causes a voltage level to be present at the out-of-phase input to be modified. The second master current source is coupled to the first master current source such that they are proportional, irrespective of environmental changes. The compensation signal generator further has a current feedback circuit connected between an output of the operational amplifier and the first master current source to sink a compensation current to the first master current source. The biasing current of the second replica amplifier and the compensating current are combined such that, as the operational amplifier changes the compensation current, the biasing current of the second replica amplifier adjusts inversely. The compensation signal generator additionally has a compensation signal converter communicating with the operational amplifier to form the compensation signal as a function of the compensating current. In the preferred implementation the compensation signal converter is a first voltage-to-current converter.
The current feedback is formed by a second voltage-to-current converter that transforms a compensating voltage at the output of the operational amplifier to the compensation current.